POWER5造句

The POWER5 architecture features the Simultaneous Multi-Threading technology.

The POWER5 chip has been designed for very high frequency operations of up to 2.0 GHz.

For example, both POWER5 and POWER6 can operate on 64-bit mode and are therefore compatible.

This emphasis was recognized and Simultaneous Multi-Threading was introduced in POWER5 systems.

Innovations in energy and cooling let it retain the same power consumption as the POWER5, while almost doubling performance.

Again, taking POWER5 as an example, the time an instruction stays in the pipeline can be divided into three parts.

In 2008, UPMC migrated over 400 LPARs from POWER5 - to POWER6-based servers, each taking less than one hour of downtime.

This important POWER5 innovation allows for the ability of one single physical processor to concurrently dispatch instructions from several hardware threads.

The POWER5 is actually the IBM second generation of dual core microprocessor chips and provides new and improved functions for more granular and flexible partitioning.

For example, several years ago, when migrating from POWER4 to POWER5, we purchased a new 9119-595 and sat it next to the old p4 p690.

To improve performance of the applications that process extensive data volumes, IBM POWER5 + processor-based systems that run AIX 5l V5.3 TL04 (or later) introduce multiple page size support.

This is one of the things that's available on a POWER5 that you can't do on a G5; you could, in theory, build your code for little-endian usage.

相同的管道结构使得为POWER4 所生成的处理器代码可以同样好地应用于基于POWER5 处理器的系统。

由于POWER5和POWER 6架构能够扩展到64位处理器，大部分应用程序都得益于2.6内核级别的NUMA支持。